The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices, and more particularly, preferred embodiments relate to semiconductor devices with a bonding pad section (an electrode for external connection) that has a characteristic structure and methods for manufacturing the same.
As semiconductor devices have been further miniaturized in recent years, wiring layers are formed in multiple layers in many more occasions. In a process for manufacturing semiconductor devices, the number of process steps for forming wiring layers and contact layers for electrically connecting the wiring layers has increased with respect to the total number of process steps required for manufacturing the semiconductor devices. Accordingly, the method for forming wiring layers and contact layers has currently become an important issue in the process for manufacturing semiconductor devices. So-called damascene methods are known among methods that facilitate the formation of wiring layers and contact layers.
In a damascene method, specified wiring grooves are formed in a dielectric layer, a wiring material such as aluminum alloy or copper is deposited in the wiring grooves, excess portions of the wiring material are polished and removed by a chemical-mechanical polishing method (hereafter referred to as a xe2x80x9cCMPxe2x80x9d method) to embed the wiring material in the wiring grooves to form wiring layers. In particular, when copper is used as the wiring material, a reactive ion etching is difficult to employ, and the use of a damascene method is considered to be more promising. Many techniques in the damascene methods have been proposed. For example, Japanese laid-open patent application HEI 11-135506 describes a method for manufacturing a bonding pad section in a wiring structure that is formed by a damascene method.
In accordance with the manufacturing method of Japanese laid-open patent application HEI 11-135506, the bonding pad section is formed in a manner described as follows. A copper wiring is formed over an uppermost dielectric layer by a damascene method. Then, a dielectric protection layer is formed over the entire surface of the dielectric layer and the copper wiring. The dielectric protection layer is patterned to form an opening section in a region where a bonding pad section is to be formed. Then, a copper oxide film on the surface of the copper wiring, which is formed during a step of removing a resist layer or a photo-etching step, is removed by a dry etching method, and then an aluminum layer is deposited thereon. Then, a selective etching is conducted to pattern the aluminum layer such that the aluminum layer covers the opening section. In this manner, the bonding pad section in which the aluminum layer is deposited is formed over the copper wiring. The reference also describes a method of depositing an aluminum layer and then removing excess portions of the aluminum layer by a CMP method to embed the aluminum layer in the opening section, instead of selectively etching and patterning the aluminum layer after the aluminum layer is deposited.
The presence of the aluminum layer over the surface of the bonding pad section provides an improved bonding property with respect to gold and the like.
However, the process described above has the following problems. When the aluminum layer is patterned by a selective etching after the copper layer is formed, the step of forming the aluminum layer, the photolithography step and the etching step are required in addition to the damascene process. This increases the number of process steps. Furthermore, the selective etching requires an etcher for aluminum layers that are not used in the damascene process. When the aluminum layer is planarized by a CMP method after the copper wiring is formed, such a CMP step is added. As a result, the number of process steps increases. Also, the process described in the reference requires a step of removing copper oxide formed on the exposed surface of the copper wiring by a gas containing oxygen plasma and hydrofluoric acid.
One embodiment relates to a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method. The method includes forming a dielectric layer in which an uppermost wiring layer is formed. The method also includes forming a wiring groove for the wiring layer having a specified pattern and an opening section for a bonding pad section in the dielectric layer. A first conduction layer is formed for the wiring layer. A second conduction layer is formed over the first conduction layer, the second conduction layer comprising a different material from that of the first conduction layer. Excess portions of the second conduction layer, the first conduction layer and the dielectric layer are removed to planarize the second conduction layer, the first conduction layer and the dielectric layer, to thereby form a wiring layer having at least the first conduction layer in the wiring groove and a bonding pad section including a base conduction layer of the first conduction layer and an exposed conduction layer of the second conduction layer in the opening section for the bonding pad section.
Another embodiment relates to a semiconductor device including a plurality of wiring layers and dielectric layers interposed between the mutual wiring layers, wherein an uppermost wiring layer and a bonding pad section are located at an identical level, and the bonding pad section includes at least a base conduction layer of a first conduction layer and an exposed conduction layer of a second conduction layer.
Another embodiment relates to a method for forming an upper wiring layer and a bonding pad in a semiconductor device, including forming an interlayer dielectric layer over a substrate, forming a mask layer over the interlayer dielectric layer, and forming an upper dielectric layer over the mask layer. The method also includes forming an upper wiring layer opening extending through the upper dielectric layer, the mask layer and the interlayer dielectric layer, and forming a bonding pad opening through the upper dielectric layer by etching through the upper dielectric layer. A first conductive material is deposited to simultaneously fill the upper wiring layer opening and partially fill the bonding pad opening. A bonding pad layer is deposited to fill the bonding pad opening, wherein the bonding pad layer is disposed over at least a portion of the first conductive material. The method also includes planarizing the device so that an upper surface of the first conductive material in the wiring layer opening and an upper surface of the bonding pad layer in the bonding pad opening are at the same level.